- read_verilog -DBOARD_ICEBREAKER=1 -I/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl -I/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40/rtl/ -I/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache/rtl/ -I/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc/rtl/ -I/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem/rtl/ -I/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb/rtl/ -I/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video/rtl/ /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_i2c_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spi_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_oserdes.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_dff.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_sync.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_match.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/i2c_master.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/i2c_master_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/muacm2wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pdm.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pwm.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/stream2wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart2wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/xclk_strobe.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/xclk_wb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_1x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_2x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_4x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_crc.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_ep_buf.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_ep_status.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_phy.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_rx_ll.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_rx_pkt.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_trans.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_tx_ll.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_tx_pkt.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_1x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_2x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_4x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_text_2x.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_shared_ram.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_text.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_palette.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_framebuf.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/sysmgr.v /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v
- synth_ice40 -dffe_min_ce_use 4 -abc9 -device u -dsp -top top -json riscv_doom.json
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