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Tobias Müller ab0c2b9772 build: Use IVERILOG variable when building simulation		пре 5 година
build	ab0c2b9772 build: Use IVERILOG variable when building simulation	пре 5 година
cores	ecab65eb7b cores/hub75: Add control signal to start/stop the panel refreshes	пре 5 година
projects	226cf1edb4 projects/rgb_panel: Fix error in fbw_data declaration	пре 5 година
.gitignore	6f6e75a6e8 Import gitignore	пре 6 година
LICENSE	e2c6a58101 Initial import of the structure and build system	пре 6 година
LICENSE.bsd	e2c6a58101 Initial import of the structure and build system	пре 6 година
LICENSE.lgpl3	e2c6a58101 Initial import of the structure and build system	пре 6 година
README.md	5bec2396e5 Fix README formatting	пре 6 година

iCE40 Playground

Collection of ip cores / modules and example projects for the Lattice iCE40 FPGA family.

Examples are often targeted for the ICEBreaker FPGA board ( https://github.com/icebreaker-fpga/icebreaker ) but some might have other / multiple targets, check their respective README / build files

Applicable license is individual to each IP core / project and is mentionnned in the IP core / example directory itself and in each file.

README.md

iCE40 Playground