Jakub Duchniewicz b7d87eaa5a Fix bridging logic. Hangups are gone. Wrong offset in register map still persits. hai 2 semanas
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3signal.v bc60e00b90 Port 3signal code and integrate to the top module. hai 3 semanas
boards.vh 67143eeaae projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0 %!s(int64=4) %!d(string=hai) anos
dfu_helper.v b5c7b7ef93 projects/riscv_usb: Update to latest dfu_helper %!s(int64=4) %!d(string=hai) anos
mailbox_wb.v 03fbd5a395 Approach fixing the overlapped mailbox registers with code and bootloader. hai 2 semanas
picorv32.v 345435957f projects/riscv_usb: Add iCE40 specific implementation of register file %!s(int64=4) %!d(string=hai) anos
picorv32_ice40_regs.v 345435957f projects/riscv_usb: Add iCE40 specific implementation of register file %!s(int64=4) %!d(string=hai) anos
soc_bram.v 637d035474 projects: Add no_rw_checks on the soc_bram instances hai 1 ano
soc_picorv32_base.v c5c853b4b2 projects: Cleanup some common code between projects %!s(int64=2) %!d(string=hai) anos
soc_picorv32_bridge.v b7d87eaa5a Fix bridging logic. Hangups are gone. Wrong offset in register map still persits. hai 2 semanas
soc_spram.v 14597759d5 projects/riscv_usb: Whitespace fixes for soc_{bram,spram} %!s(int64=4) %!d(string=hai) anos
soc_usb.v fc12f0de48 projects/riscv_usb: Move the USB stuff to a separate module %!s(int64=4) %!d(string=hai) anos
sysmgr.v 67143eeaae projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0 %!s(int64=4) %!d(string=hai) anos
top.v b7d87eaa5a Fix bridging logic. Hangups are gone. Wrong offset in register map still persits. hai 2 semanas