12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455 |
- `timescale 1ns / 1ps
- //define our module and it's inputs/outputs
- module top(
- input CLK,
- input BTN1,
- input BTN2,
- input BTN3,
- input BTN_N,
- //input [7:0] sw,
- output [4:0] led
- //output [6:0] seg,
- //output ca
- );
- reg [4:0]desired_led;
- assign led=desired_led;
- always @(posedge CLK) begin
- desired_led[0] = BTN1 & BTN2 & BTN3;
- desired_led[1] = BTN1;
- desired_led[2] = BTN2;
- desired_led[3] = BTN3;
- desired_led[4] = !BTN_N;
- end
- /*buttons buttons0(
- .CLK(CLK),
- .BTN1(BTN1),
- .BTN2(BTN2),
- .BTN3(BTN3),
- .BTN_N(BTN_N),
- .duty_val(duty_v),
- );
- duty duty0(
- .CLK(CLK),
- .cmp(duty_v),
- .out(led[0])
- );*/
- //
- // clkdiv displayClockGen(
- // .clk(CLK),
- // .clkout(displayClock)
- // );
- //
- // seven_seg_mux display(
- // .clk(displayClock),
- // .disp0(disp0),
- // .disp1(disp1),
- // .segout(seg),
- // .disp_sel(ca)
- // );
- endmodule
|