top.v 5.5 KB

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  1. /*
  2. * top.v
  3. *
  4. * vim: ts=4 sw=4
  5. *
  6. * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
  7. * SPDX-License-Identifier: CERN-OHL-P-2.0
  8. */
  9. `default_nettype none
  10. `include "boards.vh"
  11. module top (
  12. // SPI
  13. inout wire spi_mosi,
  14. inout wire spi_miso,
  15. inout wire spi_clk,
  16. output wire spi_flash_cs_n,
  17. `ifdef HAS_PSRAM
  18. output wire spi_ram_cs_n,
  19. `endif
  20. // USB TODO: remove later
  21. inout wire usb_dp,
  22. inout wire usb_dn,
  23. output wire usb_pu,
  24. // Debug UART
  25. input wire uart_rx,
  26. output wire uart_tx,
  27. // Buttons (2 for now to test up and down)
  28. input wire btn_n,
  29. input wire btn_1,
  30. input wire btn_2,
  31. // LEDs to blink to show that a value change has been registered?
  32. // GPIOs for out signal
  33. output wire out1,
  34. output wire out2,
  35. output wire out3,
  36. // LED TODO: remove later
  37. output wire [2:0] rgb,
  38. // Clock
  39. input wire clk_in
  40. );
  41. localparam integer SPRAM_AW = 14; /* 14 => 64k, 15 => 128k */
  42. localparam integer WB_N = 6;
  43. localparam integer WB_DW = 32;
  44. localparam integer WB_AW = 16;
  45. localparam integer WB_RW = WB_DW * WB_N;
  46. localparam integer WB_MW = WB_DW / 8;
  47. localparam integer FAST_PWM_WIDTH = 8;
  48. localparam integer PULSE_COUNTER_WIDTH = 8;
  49. localparam integer SLOW_PWM_WIDTH = 14;
  50. genvar i;
  51. // Signals
  52. // -------
  53. // Wishbone
  54. wire [WB_AW-1:0] wb_addr;
  55. wire [WB_DW-1:0] wb_rdata [0:WB_N-1];
  56. wire [WB_RW-1:0] wb_rdata_flat;
  57. wire [WB_DW-1:0] wb_wdata;
  58. wire [WB_MW-1:0] wb_wmsk;
  59. wire [WB_N -1:0] wb_cyc;
  60. wire wb_we;
  61. wire [WB_N -1:0] wb_ack;
  62. // WarmBoot
  63. reg boot_now;
  64. reg [1:0] boot_sel;
  65. // Clock / Reset logic
  66. wire clk_24m;
  67. wire clk_48m;
  68. wire rst;
  69. // 3 signal
  70. wire [SLOW_PWM_WIDTH-1:0] period1;
  71. wire [SLOW_PWM_WIDTH-1:0] delay1;
  72. wire [SLOW_PWM_WIDTH-1:0] duty2;
  73. wire [SLOW_PWM_WIDTH-1:0] delay2;
  74. wire [FAST_PWM_WIDTH-1:0] period3;
  75. wire [FAST_PWM_WIDTH-1:0] duty3;
  76. wire [SLOW_PWM_WIDTH-1:0] delay3;
  77. wire [PULSE_COUNTER_WIDTH-1:0] npuls3;
  78. wire [1:0] odd_train_flag;
  79. wire ena_odd_out3;
  80. // SoC
  81. // ---
  82. soc_picorv32_base #(
  83. .WB_N (WB_N),
  84. .WB_DW (WB_DW),
  85. .WB_AW (WB_AW),
  86. .SPRAM_AW(SPRAM_AW)
  87. ) base_I (
  88. .wb_addr (wb_addr),
  89. .wb_rdata(wb_rdata_flat),
  90. .wb_wdata(wb_wdata),
  91. .wb_wmsk (wb_wmsk),
  92. .wb_we (wb_we),
  93. .wb_cyc (wb_cyc),
  94. .wb_ack (wb_ack),
  95. .clk (clk_24m),
  96. .rst (rst)
  97. );
  98. for (i=0; i<WB_N; i=i+1)
  99. assign wb_rdata_flat[i*WB_DW+:WB_DW] = wb_rdata[i];
  100. // UART [1]
  101. // ----
  102. uart_wb #(
  103. .DIV_WIDTH(12),
  104. .DW(WB_DW)
  105. ) uart_I (
  106. .uart_tx (uart_tx),
  107. .uart_rx (uart_rx),
  108. .wb_addr (wb_addr[1:0]),
  109. .wb_rdata (wb_rdata[1]),
  110. .wb_we (wb_we),
  111. .wb_wdata (wb_wdata),
  112. .wb_cyc (wb_cyc[1]),
  113. .wb_ack (wb_ack[1]),
  114. .clk (clk_24m),
  115. .rst (rst)
  116. );
  117. // SPI [2]
  118. // ---
  119. ice40_spi_wb #(
  120. `ifdef HAS_PSRAM
  121. .N_CS(2),
  122. `else
  123. .N_CS(1),
  124. `endif
  125. .WITH_IOB(1),
  126. .UNIT(0)
  127. ) spi_I (
  128. .pad_mosi (spi_mosi),
  129. .pad_miso (spi_miso),
  130. .pad_clk (spi_clk),
  131. `ifdef HAS_PSRAM
  132. .pad_csn ({spi_ram_cs_n, spi_flash_cs_n}),
  133. `else
  134. .pad_csn (spi_flash_cs_n),
  135. `endif
  136. .wb_addr (wb_addr[3:0]),
  137. .wb_rdata (wb_rdata[2]),
  138. .wb_wdata (wb_wdata),
  139. .wb_we (wb_we),
  140. .wb_cyc (wb_cyc[2]),
  141. .wb_ack (wb_ack[2]),
  142. .clk (clk_24m),
  143. .rst (rst)
  144. );
  145. // RGB LEDs [3]
  146. // --------
  147. ice40_rgb_wb #(
  148. .CURRENT_MODE("0b1"),
  149. .RGB0_CURRENT("0b000001"),
  150. .RGB1_CURRENT("0b000001"),
  151. .RGB2_CURRENT("0b000001")
  152. ) rgb_I (
  153. .pad_rgb (rgb),
  154. .wb_addr (wb_addr[4:0]),
  155. .wb_rdata (wb_rdata[3]),
  156. .wb_wdata (wb_wdata),
  157. .wb_we (wb_we),
  158. .wb_cyc (wb_cyc[3]),
  159. .wb_ack (wb_ack[3]),
  160. .clk (clk_24m),
  161. .rst (rst)
  162. );
  163. // USB [4 & 5]
  164. // ---
  165. soc_usb #(
  166. .DW(WB_DW)
  167. ) usb_I (
  168. .usb_dp (usb_dp),
  169. .usb_dn (usb_dn),
  170. .usb_pu (usb_pu),
  171. .wb_addr (wb_addr[11:0]),
  172. .wb_rdata (wb_rdata[4]),
  173. .wb_wdata (wb_wdata),
  174. .wb_we (wb_we),
  175. .wb_cyc (wb_cyc[5:4]),
  176. .wb_ack (wb_ack[5:4]),
  177. .clk_sys (clk_24m),
  178. .clk_48m (clk_48m),
  179. .rst (rst)
  180. );
  181. assign wb_rdata[5] = 0;
  182. // 3 Signal
  183. // --------
  184. three_signal #(
  185. .FAST_PWM_WIDTH(FAST_PWM_WIDTH),
  186. .PULSE_COUNTER_WIDTH(PULSE_COUNTER_WIDTH),
  187. .SLOW_PWM_WIDTH(SLOW_PWM_WIDTH)
  188. ) three_signal_I(
  189. .nrst(~rst),
  190. .clk(clk_48m),
  191. .period1(period1),
  192. .delay1(delay1),
  193. .duty2(duty2),
  194. .delay2(delay2),
  195. .period3(period3),
  196. .duty3(duty3),
  197. .delay3(delay3),
  198. .npuls3(npuls3),
  199. .odd_train_flag(odd_train_flag),
  200. .ena_odd_out3(ena_odd_out3),
  201. .Out1(out1),
  202. .Out2(out2),
  203. .Out3(out3)
  204. );
  205. // Warm Boot
  206. // ---------
  207. // Bus interface
  208. always @(posedge clk_24m or posedge rst)
  209. if (rst) begin
  210. boot_now <= 1'b0;
  211. boot_sel <= 2'b00;
  212. end else if (wb_cyc[0] & wb_we & (wb_addr[2:0] == 3'b000)) begin
  213. boot_now <= wb_wdata[2];
  214. boot_sel <= wb_wdata[1:0];
  215. end
  216. assign wb_rdata[0] = 0;
  217. assign wb_ack[0] = wb_cyc[0];
  218. // Helper
  219. dfu_helper #(
  220. .TIMER_WIDTH(24),
  221. .BTN_MODE(3),
  222. .DFU_MODE(0)
  223. ) dfu_helper_I (
  224. .boot_now(boot_now),
  225. .boot_sel(boot_sel),
  226. .btn_pad(btn_n),
  227. .btn_val(),
  228. .rst_req(),
  229. .clk(clk_24m),
  230. .rst(rst)
  231. );
  232. // Clock / Reset
  233. // -------------
  234. `ifdef SIM
  235. reg clk_48m_s = 1'b0;
  236. reg clk_24m_s = 1'b0;
  237. reg rst_s = 1'b1;
  238. always #10.42 clk_48m_s <= !clk_48m_s;
  239. always #20.84 clk_24m_s <= !clk_24m_s;
  240. initial begin
  241. #200 rst_s = 0;
  242. end
  243. assign clk_48m = clk_48m_s;
  244. assign clk_24m = clk_24m_s;
  245. assign rst = rst_s;
  246. `else
  247. sysmgr sys_mgr_I (
  248. .clk_in(clk_in),
  249. .rst_in(1'b0),
  250. .clk_48m(clk_48m),
  251. .clk_24m(clk_24m),
  252. .rst_out(rst)
  253. );
  254. `endif
  255. endmodule // top