| .. |
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3signal.v
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bc60e00b90
Port 3signal code and integrate to the top module.
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3 周之前 |
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boards.vh
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67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
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4 年之前 |
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dfu_helper.v
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b5c7b7ef93
projects/riscv_usb: Update to latest dfu_helper
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4 年之前 |
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picorv32.v
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345435957f
projects/riscv_usb: Add iCE40 specific implementation of register file
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4 年之前 |
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picorv32_ice40_regs.v
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345435957f
projects/riscv_usb: Add iCE40 specific implementation of register file
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4 年之前 |
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soc_bram.v
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637d035474
projects: Add no_rw_checks on the soc_bram instances
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1 年之前 |
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soc_picorv32_base.v
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c5c853b4b2
projects: Cleanup some common code between projects
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2 年之前 |
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soc_picorv32_bridge.v
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6480c5c26b
projects/riscv_usb: Rename bridge to soc_picorv32_bridge + WS fixes
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4 年之前 |
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soc_spram.v
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14597759d5
projects/riscv_usb: Whitespace fixes for soc_{bram,spram}
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4 年之前 |
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soc_usb.v
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fc12f0de48
projects/riscv_usb: Move the USB stuff to a separate module
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4 年之前 |
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sysmgr.v
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67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
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4 年之前 |
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top.v
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bc60e00b90
Port 3signal code and integrate to the top module.
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3 周之前 |
Jakub Duchniewicz
bc60e00b90
Port 3signal code and integrate to the top module.