bridge.v 4.0 KB

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  1. /*
  2. * bridge.v
  3. *
  4. * vim: ts=4 sw=4
  5. *
  6. * Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
  7. * All rights reserved.
  8. *
  9. * BSD 3-clause, see LICENSE.bsd
  10. *
  11. * Redistribution and use in source and binary forms, with or without
  12. * modification, are permitted provided that the following conditions are met:
  13. * * Redistributions of source code must retain the above copyright
  14. * notice, this list of conditions and the following disclaimer.
  15. * * Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * * Neither the name of the <organization> nor the
  19. * names of its contributors may be used to endorse or promote products
  20. * derived from this software without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  23. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25. * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  26. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. */
  33. `default_nettype none
  34. module bridge #(
  35. parameter integer WB_N = 8,
  36. parameter integer WB_DW = 32,
  37. parameter integer WB_AW = 16,
  38. parameter integer WB_AI = 2
  39. )(
  40. /* PicoRV32 bus */
  41. input wire [31:0] pb_addr,
  42. output wire [31:0] pb_rdata,
  43. input wire [31:0] pb_wdata,
  44. input wire [ 3:0] pb_wstrb,
  45. input wire pb_valid,
  46. output wire pb_ready,
  47. /* BRAM */
  48. output wire [ 7:0] bram_addr,
  49. input wire [31:0] bram_rdata,
  50. output wire [31:0] bram_wdata,
  51. output wire [ 3:0] bram_wmsk,
  52. output wire bram_we,
  53. /* SPRAM */
  54. output wire [13:0] spram_addr,
  55. input wire [31:0] spram_rdata,
  56. output wire [31:0] spram_wdata,
  57. output wire [ 3:0] spram_wmsk,
  58. output wire spram_we,
  59. /* Wishbone buses */
  60. output wire [WB_AW-1:0] wb_addr,
  61. output wire [WB_DW-1:0] wb_wdata,
  62. input wire [(WB_DW*WB_N)-1:0] wb_rdata,
  63. output wire [WB_N-1:0] wb_cyc,
  64. output wire wb_we,
  65. input wire [WB_N-1:0] wb_ack,
  66. /* Clock / Reset */
  67. input wire clk,
  68. input wire rst
  69. );
  70. // Signals
  71. // -------
  72. wire ram_sel;
  73. reg ram_rdy;
  74. wire [31:0] ram_rdata;
  75. reg [31:0] wb_rdata_or;
  76. wire wb_rdy;
  77. // RAM access
  78. // ----------
  79. // BRAM : 0x00000000 -> 0x000003ff
  80. // SPRAM : 0x00010000 -> 0x0001ffff
  81. assign bram_addr = pb_addr[ 9:2];
  82. assign spram_addr = pb_addr[15:2];
  83. assign bram_wdata = pb_wdata;
  84. assign spram_wdata = pb_wdata;
  85. assign bram_wmsk = pb_wstrb;
  86. assign spram_wmsk = pb_wstrb;
  87. assign bram_we = pb_valid & ~pb_addr[31] & |pb_wstrb & ~pb_addr[16];
  88. assign spram_we = pb_valid & ~pb_addr[31] & |pb_wstrb & pb_addr[16];
  89. assign ram_rdata = ~pb_addr[31] ? (pb_addr[16] ? spram_rdata : bram_rdata) : 32'h00000000;
  90. assign ram_sel = pb_valid & ~pb_addr[31];
  91. always @(posedge clk)
  92. ram_rdy <= ram_sel && ~ram_rdy;
  93. // Wishbone
  94. // --------
  95. // wb[x] = 0x8x000000 - 0x8xffffff
  96. genvar i;
  97. assign wb_addr = pb_addr[WB_AW+WB_AI-1:WB_AI];
  98. assign wb_wdata = pb_wdata[WB_DW-1:0];
  99. assign wb_we = |pb_wstrb;
  100. for (i=0; i<WB_N; i=i+1)
  101. assign wb_cyc[i] = pb_valid & pb_addr[31] & (pb_addr[27:24] == i);
  102. assign wb_rdy = |wb_ack;
  103. always @(*)
  104. begin : wb_or
  105. integer i;
  106. wb_rdata_or = 0;
  107. for (i=0; i<WB_N; i=i+1)
  108. wb_rdata_or[WB_DW-1:0] = wb_rdata_or[WB_DW-1:0] | wb_rdata[WB_DW*i+:WB_DW];
  109. end
  110. // Final data combining
  111. // --------------------
  112. assign pb_rdata = ram_rdata | wb_rdata_or;
  113. assign pb_ready = ram_rdy | wb_rdy;
  114. endmodule // bridge