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Sylvain Munaut c1483f3018 projects/riscv_usb: Update BOARD define for C source to match verilog one		vor 4 Jahren
build	786919b165 build: Remove the -relut yosys option	vor 4 Jahren
cores	c138c61984 cores/e1: Add option to use an external LIU instead of the iCE40 as PHY	vor 4 Jahren
projects	c1483f3018 projects/riscv_usb: Update BOARD define for C source to match verilog one	vor 4 Jahren
.gitignore	6f6e75a6e8 Import gitignore	vor 6 Jahren
LICENSE	e2c6a58101 Initial import of the structure and build system	vor 6 Jahren
LICENSE.bsd	e2c6a58101 Initial import of the structure and build system	vor 6 Jahren
LICENSE.lgpl3	e2c6a58101 Initial import of the structure and build system	vor 6 Jahren
README.md	5bec2396e5 Fix README formatting	vor 6 Jahren

iCE40 Playground

Collection of ip cores / modules and example projects for the Lattice iCE40 FPGA family.

Examples are often targeted for the ICEBreaker FPGA board ( https://github.com/icebreaker-fpga/icebreaker ) but some might have other / multiple targets, check their respective README / build files

Applicable license is individual to each IP core / project and is mentionnned in the IP core / example directory itself and in each file.

README.md

iCE40 Playground