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doom_riscv
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Sylvain Munaut c1483f3018 projects/riscv_usb: Update BOARD define for C source to match verilog one 4 anos atrás
build 786919b165 build: Remove the -relut yosys option 4 anos atrás
cores c138c61984 cores/e1: Add option to use an external LIU instead of the iCE40 as PHY 4 anos atrás
projects c1483f3018 projects/riscv_usb: Update BOARD define for C source to match verilog one 4 anos atrás
.gitignore 6f6e75a6e8 Import gitignore 6 anos atrás
LICENSE e2c6a58101 Initial import of the structure and build system 6 anos atrás
LICENSE.bsd e2c6a58101 Initial import of the structure and build system 6 anos atrás
LICENSE.lgpl3 e2c6a58101 Initial import of the structure and build system 6 anos atrás
README.md 5bec2396e5 Fix README formatting 6 anos atrás

README.md

iCE40 Playground

Collection of ip cores / modules and example projects for the Lattice iCE40 FPGA family.

Examples are often targeted for the ICEBreaker FPGA board ( https://github.com/icebreaker-fpga/icebreaker ) but some might have other / multiple targets, check their respective README / build files

Applicable license is individual to each IP core / project and is mentionnned in the IP core / example directory itself and in each file.