sysmgr.v 3.1 KB

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  1. /*
  2. * sysmgr.v
  3. *
  4. * vim: ts=4 sw=4
  5. *
  6. * Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
  7. * All rights reserved.
  8. *
  9. * BSD 3-clause, see LICENSE.bsd
  10. *
  11. * Redistribution and use in source and binary forms, with or without
  12. * modification, are permitted provided that the following conditions are met:
  13. * * Redistributions of source code must retain the above copyright
  14. * notice, this list of conditions and the following disclaimer.
  15. * * Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * * Neither the name of the <organization> nor the
  19. * names of its contributors may be used to endorse or promote products
  20. * derived from this software without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  23. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25. * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  26. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. */
  33. `default_nettype none
  34. `include "boards.vh"
  35. module sysmgr (
  36. input wire clk_in,
  37. input wire rst_in,
  38. output wire clk_24m,
  39. output wire clk_48m,
  40. output wire rst_out
  41. );
  42. // Signals
  43. wire pll_lock;
  44. wire pll_reset_n;
  45. wire clk_24m_i;
  46. wire clk_48m_i;
  47. wire rst_i;
  48. reg [3:0] rst_cnt;
  49. // PLL instance
  50. `ifdef PLL_CORE
  51. SB_PLL40_2F_CORE #(
  52. `else
  53. SB_PLL40_2F_PAD #(
  54. `endif
  55. .DIVR(`PLL_DIVR),
  56. .DIVF(`PLL_DIVF),
  57. .DIVQ(`PLL_DIVQ),
  58. .FILTER_RANGE(`PLL_FILTER_RANGE),
  59. .FEEDBACK_PATH("SIMPLE"),
  60. .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
  61. .FDA_FEEDBACK(4'b0000),
  62. .SHIFTREG_DIV_MODE(2'b00),
  63. .PLLOUT_SELECT_PORTA("GENCLK"),
  64. .PLLOUT_SELECT_PORTB("GENCLK_HALF"),
  65. .ENABLE_ICEGATE_PORTA(1'b0),
  66. .ENABLE_ICEGATE_PORTB(1'b0)
  67. ) pll_I (
  68. `ifdef PLL_CORE
  69. .REFERENCECLK(clk_in),
  70. `else
  71. .PACKAGEPIN(clk_in),
  72. `endif
  73. .PLLOUTCOREA(),
  74. .PLLOUTGLOBALA(clk_48m_i),
  75. .PLLOUTCOREB(),
  76. .PLLOUTGLOBALB(clk_24m_i),
  77. .EXTFEEDBACK(1'b0),
  78. .DYNAMICDELAY(8'h00),
  79. .RESETB(pll_reset_n),
  80. .BYPASS(1'b0),
  81. .LATCHINPUTVALUE(1'b0),
  82. .LOCK(pll_lock),
  83. .SDI(1'b0),
  84. .SDO(),
  85. .SCLK(1'b0)
  86. );
  87. assign clk_24m = clk_24m_i;
  88. assign clk_48m = clk_48m_i;
  89. // PLL reset generation
  90. assign pll_reset_n = ~rst_in;
  91. // Logic reset generation
  92. always @(posedge clk_24m_i or negedge pll_lock)
  93. if (!pll_lock)
  94. rst_cnt <= 4'h0;
  95. else if (~rst_cnt[3])
  96. rst_cnt <= rst_cnt + 1;
  97. assign rst_i = ~rst_cnt[3];
  98. SB_GB rst_gbuf_I (
  99. .USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i),
  100. .GLOBAL_BUFFER_OUTPUT(rst_out)
  101. );
  102. endmodule // sysmgr