Jakub Duchniewicz 506cdd9e8d Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW. 11 hodín pred
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3signal.v 2ba5998af1 freq increase voodoo 13 hodín pred
boards.vh 67143eeaae projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0 4 rokov pred
button.v a310b26df0 add initial version of button logic + dummy usage 5 dní pred
dfu_helper.v b5c7b7ef93 projects/riscv_usb: Update to latest dfu_helper 4 rokov pred
mailbox_wb_rtl2sw.v 506cdd9e8d Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW. 11 hodín pred
mailbox_wb_sw2rtl.v 506cdd9e8d Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW. 11 hodín pred
picorv32.v 345435957f projects/riscv_usb: Add iCE40 specific implementation of register file 4 rokov pred
picorv32_ice40_regs.v 345435957f projects/riscv_usb: Add iCE40 specific implementation of register file 4 rokov pred
soc_bram.v 637d035474 projects: Add no_rw_checks on the soc_bram instances 1 rok pred
soc_picorv32_base.v 30e995fcc2 Add timer expiring in SW. 4 dní pred
soc_picorv32_bridge.v b7d87eaa5a Fix bridging logic. Hangups are gone. Wrong offset in register map still persits. 2 týždňov pred
soc_spram.v 14597759d5 projects/riscv_usb: Whitespace fixes for soc_{bram,spram} 4 rokov pred
soc_usb.v fc12f0de48 projects/riscv_usb: Move the USB stuff to a separate module 4 rokov pred
sysmgr.v 67143eeaae projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0 4 rokov pred
top.v 506cdd9e8d Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW. 11 hodín pred