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delay.v
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68ac87f6c4
Update the vim modeline to be closer to top of file
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пре 6 година |
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fifo_sync_ram.v
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ffcdd3ac1e
cores/misc: Import a couple of Synchronous FIFO options
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пре 6 година |
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fifo_sync_shift.v
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ffcdd3ac1e
cores/misc: Import a couple of Synchronous FIFO options
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пре 6 година |
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glitch_filter.v
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68ac87f6c4
Update the vim modeline to be closer to top of file
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пре 6 година |
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pdm.v
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57373928b0
cores/misc: Import simple PDM core (pulse density modulation)
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пре 5 година |
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prims.v
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68ac87f6c4
Update the vim modeline to be closer to top of file
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пре 6 година |
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pwm.v
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68ac87f6c4
Update the vim modeline to be closer to top of file
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пре 6 година |
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ram_sdp.v
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68ac87f6c4
Update the vim modeline to be closer to top of file
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пре 6 година |
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uart_rx.v
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2ed6b32cf4
cores/misc: Add simple UART TX/RX cores
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пре 6 година |
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uart_tx.v
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2ed6b32cf4
cores/misc: Add simple UART TX/RX cores
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пре 6 година |
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uart_wb.v
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5e7d05e3e7
cores/misc: Fix uart_wb handling of full fifo
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пре 5 година |
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xclk_strobe.v
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6067f61535
cores/misc: Add cross-clock strobe
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пре 6 година |
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xclk_wb.v
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2e0e25b76f
cores/misc: Add cross-clock wishbone interface
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пре 6 година |
Sylvain Munaut
5e7d05e3e7
cores/misc: Fix uart_wb handling of full fifo