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Jakub Duchniewicz bc60e00b90 Port 3signal code and integrate to the top module. 3 weeks ago
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clocks.py 903ae87b18 projects/riscv_usb: Set clock to their real frequency 4 years ago
top-bitsy-v0.pcf 7c7e120a84 projects: Update constraints for bitsy v0 and v1 4 years ago
top-bitsy-v1.pcf 7c7e120a84 projects: Update constraints for bitsy v0 and v1 4 years ago
top-icebreaker.pcf bc60e00b90 Port 3signal code and integrate to the top module. 3 weeks ago