jduchniewicz/doom_riscv @ f649acd3035e8909eed419555360174e276dd312

Sylvain Munaut f33e481214 build: When creating verilog define for board name, replace - with _		5 роки тому
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core-magic.mk	b90e522d72 build: Allow 'simulation sources' in cores and projects	6 роки тому
core-rules.mk	4812ab7b22 build: Add explicit include directory for the rtl/ & sim/ dir of each core	6 роки тому
project-rules.mk	f33e481214 build: When creating verilog define for board name, replace - with _	5 роки тому