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doom_riscv
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Sylvain Munaut fc989e8582 cores/usb: Capture CEL state at transaction start vor 5 Jahren
build f33e481214 build: When creating verilog define for board name, replace - with _ vor 5 Jahren
cores fc989e8582 cores/usb: Capture CEL state at transaction start vor 5 Jahren
projects 14dfdcad90 projects/hdmi_test: Update the PCFs with other options vor 5 Jahren
.gitignore 6f6e75a6e8 Import gitignore vor 6 Jahren
LICENSE e2c6a58101 Initial import of the structure and build system vor 6 Jahren
LICENSE.bsd e2c6a58101 Initial import of the structure and build system vor 6 Jahren
LICENSE.lgpl3 e2c6a58101 Initial import of the structure and build system vor 6 Jahren
README.md 5bec2396e5 Fix README formatting vor 6 Jahren

README.md

iCE40 Playground

Collection of ip cores / modules and example projects for the Lattice iCE40 FPGA family.

Examples are often targeted for the ICEBreaker FPGA board ( https://github.com/icebreaker-fpga/icebreaker ) but some might have other / multiple targets, check their respective README / build files

Applicable license is individual to each IP core / project and is mentionnned in the IP core / example directory itself and in each file.