#!/bin/bash

# Set variables
TOP_MODULE="top"
TESTBENCH="src/top_tb.cpp"
VERILATED_DIR="obj_dir"

# Run Verilator to compile Verilog code into C++ simulation
verilator --cc src/$TOP_MODULE.v --exe $TESTBENCH --trace

# Build the simulation executable
make -C obj_dir -f V$TOP_MODULE.mk V$TOP_MODULE

# Run the compiled simulation
./obj_dir/V$TOP_MODULE